1. Field of the Invention
The present disclosure generally relates to the field of semiconductor manufacturing, and, more particularly, to the formation of contact elements directly connecting to a circuit element.
2. Description of the Related Art
Semiconductor devices, such as advanced integrated circuits, typically contain a great number of circuit elements, such as transistors, capacitors, resistors and the like, which are usually formed in a substantially planar configuration on an appropriate substrate having formed thereon a semiconductor layer. Due to the high number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements may generally not be established within the same level on which the circuit elements are manufactured, but require a plurality of additional “wiring” layers, which are also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and also include a plurality of inter-level connections, which are also referred to as “vias,” that are filled with an appropriate metal and provide the electrical connection between two neighboring stacked metallization layers.
Due to the continuous reduction of the feature sizes of circuit elements in modern integrated circuits, the number of circuit elements for a given chip area, that is, the packing density, also increases, thereby necessitating an adequate number of electrical connections to provide the desired circuit functionality. Therefore, the number of stacked metallization layers usually increases as the number of circuit elements per chip area becomes larger, while nevertheless the sizes of individual metal lines and vias are reduced.
Similarly, the contact structure of the semiconductor device, which may be considered as an interface connecting the circuit elements of the device level with the metallization system, has to be adapted to the reduced feature sizes in the device level and the metallization system. For this reason, very sophisticated patterning strategies may have to be applied in order to provide the contact elements with the required density and with appropriate reduced dimensions, at least at the device level side, in order to appropriately connect to the contact regions, such as drain and source regions, gate electrode structures and the like, without contributing to pronounced leakage current paths and even short circuits and the like. In many conventional approaches, the contact elements or contact plugs are typically formed by using a tungsten-based metal together with an interlayer dielectric stack that is typically comprised of silicon dioxide in combination with an etch stop material, such as a silicon nitride material. Due to the very reduced critical dimensions of the circuit elements, such as the transistors, the respective contact elements have to be formed on the basis of contact openings with an aspect ratio which may be as high as approximately 8:1 or more, wherein a diameter of the contact openings may be 0.1 μm or significantly less for transistor devices of, for instance, the 65 nm technology node. In even further sophisticated approaches, and in very densely packed device regions, the width of the contact openings may be 50 nm and less. Generally, an aspect ratio of such contact openings may be defined as the ratio of the depth of the opening relative to the width of the opening.
Hence, after providing the contact opening with the required minimum width, an appropriate conductive material, such as tungsten in combination with an appropriate barrier layer system, has to be deposited, which may typically be accomplished on the basis of sputter deposition technique, for instance, for the barrier materials and chemical vapor deposition (CVD)-like process recipes for forming the tungsten material.
Upon further reducing the critical dimensions of transistor elements, the complexity of the patterning process, i.e., of the lithography process and the subsequent etch process, may result in severe contact failures when densely packed device regions are considered. For example, in densely packed device regions, transistors, and thus gate electrode structures, have to be positioned close to each other in view of the corresponding design requirements, wherein drain and source regions may have to be contacted between the closely spaced gate electrode structures. Consequently, the patterning process has to provide contact openings with a lateral width that is less than the spacing between closely spaced gate electrode structures, while at the same time a high degree of accuracy in appropriately aligning the corresponding etch mask may result in extremely reduced process margins. Thus, even minute misalignments of the lateral position of an etch mask with respect to the gate electrode structures may result in an exposure of gate electrode material during the subsequent complex etch process, which will finally result in a short circuit between the contact element and the adjacent gate electrode structure.
Consequently, in view of enhancing the reliability of the manufacturing process and the resulting contact elements of semiconductor devices, in particular in view of contacts that have to connect to the active semiconductor region in areas comprising closely spaced gate electrode structures, the final width of contact openings may be defined on the basis of an additional deposition process in which a liner material, such as a silicon dioxide material, may be formed in the contact opening, for instance prior to etching through an etch stop layer, thereby reliably covering any exposed portions of gate electrode structures and also providing an efficient etch mask of reduced width for etching through the contact etch stop layer in order to reliably connect to the contact region in the active semiconductor region. Hence, the resolution of well-established lithography techniques and patterning strategies may be refined by forming the silicon dioxide liner material in the contact openings prior to performing a final etch step, thereby reducing the probability of creating short circuits between contact elements and adjacent gate electrode structures. On the other hand, the overall contact resistivity may be increased due to the reduced cross-sectional area of the contact elements, which may particularly negatively affect contact elements which are positioned in less critical device regions. For example, contact elements connecting to the contact areas of gate electrode structures may be less critical with respect to misalignments and short circuits which, however, may suffer from a significantly increased contact resistivity, thereby contributing to an overall reduced performance of a contact level of the semiconductor device.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.